Have Your Say — Join a Dassault Systèmes Semiconductor User Group Meeting

By Matthew
Semiconductor User Day Venues

 

Given the success of last year’s Semiconductor User Group meeting held at the DS HQ in Vélizy, France, we have decided to continue to do it again and this year, we will also hold a 2-day meeting in the USA this September in addition to a sister meeting that will take place in October again at the DS HQ in France.

Here’s what you can look forward to experiencing:

Day 1: Silicon Thinking – Turning Semiconductor Complexity into Business ProfitabilityWorkshopVelizy

  • Now, engineering teams can take an active role in helping their companies achieve profitability
  • See how Silicon Thinking delivers a collaborative business platform that brings design teams, manufacturing teams, and product engineering teams  together for the first time

Day 2: Semiconductor Connection Day
* Note: day 2 is designed for current ENOVIA semiconductor users

  • Spend time with Dassault Semiconductor Solution R&D in a round table environment
  • Learn about the latest developments, share customers success stories and influence the Semiconductor Solution development roadmap

 So where and when is this event happening?

NAM: Computer History Museum, Mountain View, CA

September 15-16 Register Now!

EMEA: 3DS Paris Campus, Velizy, France

October 22-23 Register Now!

Matthew J. HallMatthew Hall is the ENOVIA User Advocacy & Social EXPERIENCE Specialist.  You can find him on Twitter at @mjhall. Connect with ENOVIA at @3DSENOVIA

Factors Affecting the Future of the Semiconductor IP Management Business

By Eric

The era of semiconductor IP is here and it’s a good sized business.  (>£700M for ARM, >$400M for Synopsys, > $100M for Cadence, all annually)  And without a doubt, the demand for semiconductor IP will continue to grow. Regardless of the size of the target market, all companies creating semiconductors are now using or reusing IP, whether developed internally or externally. But a variety of business factors will shape the future of the IP business.

Sourced from: http://bit.ly/YxXx3F

The success of leading device manufacturers in dreaming up new, more advanced features and capabilities which consumers seem to want and buy drives semiconductors to be ever more complex and short lived. This affects the nature of IP. For example, short life cycles mean less business value which then affects investment in quality, both by the IP provider and licensee. Quality is gained through the V&V process as well as development support. It’s highly likely that IP providers and consumers that have differentiated V&V know-how and support systems will have an edge in the market. Similarly, the ability to capture and manage specs and know-how for IP block integration will be a differentiator.

The larger device designers who are market leaders will have economies of scale working in their favor, allowing differentiated advancements in power consumption and functionality through finer-grain integration of IP blocks. They can absorb the additional V&V and design costs from stitching hundreds of IP blocks into a system. And in fact it’s highly likely that these companies will continue to be the primary consumers of IP, because they can gain the most value from it. But, as advances in differentiation slow in a particular product category (witness pocket calculators), this advantage may recede. Smaller vendors who from the start become adept at on-boarding, managing and reusing IP, especially larger sub-systems may gain advantage over time through constant refinement of development and IP licensing processes to maximize margins despite smaller served markets.

In summary, there are a number of factors, some of them opposing each other which will affect the business for creation and consumption of semiconductor IP. Businesses that adapt to these factors, and implement processes and systems to streamline their IP management will fair better against the external forces that work against them. In some ways, it’s a lot like being chased by a bear: you don’t have to run faster than the bear, only faster than the guy next to you.

More information about Dassault Systemes solutions for IP Management. 

Enhancing Semiconductor Design/Manufacturing Collaboration

By Eric

Whether for a single customer or a larger market, investing in new semiconductor products is a high risk business with the potential for strong profitability, but also significant loss. Mitigating risks in the manufacturing process go a long way in assuring that those business investments are profitable. Risk mitigation can be done through comprehensive automation of the collaboration between engineering to manufacturing.  A number of benefits accrue through automation:

  • Consistent use of best practice know-how
  • Reduction of ECO costs  from best-practice process deviations
  • Enhanced oversight and compliance for material and chemical content reporting
  • Acceleration of product introduction time
  • Faster, lower cost accommodation for unexpected supply chain change decisions

 

This automation requires an integrated approach to configuring and managing the sourcing network as it applies to the IC BOM. The notion of an inverted IC BOM (see figure below) provides a model for defining the steps from which a wafer then is transformed into integrated circuit parts inventory. This becomes especially important when singulated dies find their way into a wide variety of finished goods SKUs.

IC BOM Example

The automation of this process is best done using a configurable rules system and process definition editor that creates hierarchical process that defines the execution of wafer-to-parts transformation. That transformation must not only embody best possible scenario that maximizes profitability, but also be configurable to accommodate unforeseen business and technical factors that require deviation from best business case in order to meet customer commitments. It should also  accommodate corrective workflows for possible process deviation errors.

The rules engine should be able to define the complete sourcing network including fabrication, bumping, singulation, assembly, sorting, testing, marking and inventory storage and shipment. Process managers should be able to create and change these processes without resorting to low-level IT coding support, so as to quickly respond to supply chain issues. The resulting process should also provide up-to-date requirements and test result traceability from NPI to manufacturing. It should include  analytics for flexible, end-user configurable assessment of process performance.

This process engine is then the structure for distributing manufacturing requirements and instructions, collecting test and operational data, creating a single go-to resource for design-to-manufacturing oversight.

Come visit us at the Design Automation Conference in San Francisco next week where our process architects for design-to-manufacturing process coordination will be discussing and demonstrating solutions and best-practices. We’ll be offering a full presentation and demo agenda, a cocktail hour and prizes.



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